K. Jagannadha Naidu ¹, Harish M. Kittur ¹

Affiliations
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Objectives: A novel On Chip switched capacitor architecture to produce multiple voltages with high switching frequency and low ripple voltage. Methods: The proposed architecture uses integration of more than one converter topology to produce the scalable output voltage. The converter consists of MOSFET switches and MOS charge-transfer capacitors. The control circuitry was designed completely with digital domain to reduce static power consumed. Findings:The simulation of the scalable DC-DC converter was performed using TSMC 90nm Technology .The maximal efficiency of 80% was achieved for different topologies with 364 MHz switching frequency. Improvements: The load driving capacity of this converter was up to 5uW.

Keywords

DC-DC, DVS, High Frequency, Ripple Voltage, Voltage Converter

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K. Jagannadha Naidu ¹, M. Srikanth ¹

Affiliations
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Objective:Verification of the Slave block in Ethernet Management Interface using UVM.  Methodology:Management data input output (MDIO) and Management data clock (MDC) is a two-wire interface used by Ethernet Station Management Entity to configure as well as read status from various PHY devices connected to it. Universal verification methodology is used to verify integrated designs. Verification of the Slave block in Ethernet Management Interface is done through UVM. Findings: Verification environment for the Slave Block in Ethernet Management Interface is built using UVM. 94.44% functional coverage and 97.96 code coverage is achieved. Applications: Ethernet protocol is used in the computer communication.

Keywords

Ethernet Management Interface, System Verilog, UVM, Verification

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